In order to save processing cost and reduce cell size, it has become a common practice to incorporate ("embed") analog circuits such as capacitors to nonvolatile memory cells such as EPROM, EEPROM, and flash memories. The so-called embedded memory cells can be and have been advantageously used in many applications such as in making telecommunication equipment, especially in the manufacturing of light-weight wireless phones. Another important application is to incorporate DRAM cells, each of which typically contains a single transistor and a single capacitor, into a flash memory.
Conventional embedded flash memory cells typically assume a three-polysilicon structure, with the first and second polysilicon layers, along with an oxide/nitride/oxide (ONO) layer, forming the stacked or split gate portion of the embedded structure, and with the second and third polysilicon layers, along with a capacitor dielectric layer, forming the capacitor portion of the embedded structure. Such a three-polysilicon structure is necessary because of the different levels of doping required of the floating gate and of the bottom electrode. On the one hand, the doping level of both of the two polysilicon electrodes of the capacitor portion should preferably be very high in order to avoid the possible degradation of capacitor voltage coefficient due to the parasitic depletion of capacitance inside the polysilicon films. On the other hand, the floating gate is usually lightly doped to ensure the quality and reliability of the gate oxide beneath the floating gate, and of the interpoly dielectric (e.g., the ONO layer) formed between the floating gate and the control gate.
Because of the requirement of a very highly doped polysilicon electrode for the capacitor, the first polysilicon formed for forming the floating gate cannot be used as the base for forming the bottom electrode of the capacitor. As a result, the bottom capacitor must be, at the best, made from the second polysilicon, and a third polysilicon must be formed to serve as the top capacitor electrode. Thus, an embedded nonvolatile memory device for analog applications will involve a triple-polysilicon structure, and a capacitor interpoly dielectric is sandwiched between the highly doped second and third polysilicons. The second polysilicon serves both as the control gate of the memory cell, as well as the bottom electrode of the integrally embedded capacitor. And the "extra" third polysilicon serves as the top electrode of the capacitor. Such triple-polysilicon structure embedded nonvolatile memory device, inevitably results in substantially increased processing cost as well as process complexity.
U.S. Pat. No. 5,563,762 discloses a capacitor structure for an integrated circuit which comprises a bottom electrode, capacitor dielectric and top electrode formed on a passivation layer overlying the interconnect metallization. The capacitor electrodes are interconnected to the underlying integrated circuit from underneath, through conductive vias, to the underlying interconnect metallization. The passivation layer serves as a barrier layer for a ferroelectric dielectric. Large area on-chip capacitors can be added without affecting the interconnect routing or packing density of the underlying devices.
U.S. Pat. No. 5,359,216 discloses a method for fabricating DRAM cells having an upper capacitor plate over a polysilicon storage gate. The built-in capacitor contains a dielectric which is formed as an oxide-nitride composite then reoxided, so as to provide a very high specific capacitance and very good integrity between the first poly storage gate and the (second or third poly) upper capacitor plate. The structure provides the advantages of high dielectric integrity, high specific capacitance, uniformity and reproducibility.
U.S. Pat. No. 4,818,711 discloses a method for growing a high quality oxide layer on the surface of a polysilicon film for use as an interpoly dielectric. The method comprises the steps of depositing a silicon film on a wafer and implanting the silicon film with phosphorous ions. The wafers are then sent into a diffusion tube to activate the dopant. The operation is carried out in an ambient of dry oxygen so as cause the silicon film to become polysilicon film and an oxide layer formed on the polysilicon film. The wafers are then implanted, through the oxide layer, using argon ions to cause the surface layers of the polysilicon layer to be rendered amorphous. The oxide layer grown on the polysilicon film is then removed, and a new oxide layer is then grown on the polysilicon film which exhibits excellent physical and electrical characteristics.
U.S. Pat. No. 4,882,649 discloses an integrated circuit capacitor with improved leakage and storage characteristics. It contains a dielectric material which consists of a first layer of silicon nitride adjacent the silicon substrate lower plate upon which a layer of silicon dioxide is formed. A second layer of silicon nitride is formed over the silicon dioxide layer, above which the second plate is formed. The layer of silicon dioxide can be formed by partial oxidation of the first silicon nitride layer.
The above patents give examples of some of the research work that has been done in the industry relating to embedded flash memory cells. However, none of the research efforts taught the fabrication of flash memory cells involving a two-polysilicon structure.
U.S. Pat. No. 5,442,210 discloses a semiconductor device which contains a DRAM portion forming a cache memory and a flash memory portion fabricated on a common substrate. A bottom electrode layer common to the capacitors of the DRAM portion and a floating gate layer of the flash memory portion are formed simultaneously from the same first polysilicon layer (poly1), and a top electrode layer common to the capacitors of the DRAM portion, a gate electrode layer for a transistor of the DRAM portion, and a control gate layer of the flash memory portion are formed simultaneously from the same second polysilicon layer (poly2). The technique disclosed in the '210 patent can be utilized to fabricate two-polysilicon structured embedded flash memory. However, because the bottom electrode layer and the floating gate of the embedded structure have the same doping level, the embedded flash memory cell will likely to have either an unsatisfactory capacitor portion or an unsatisfactory memory portion, or both. Indeed, the two-polysilicon structure disclosed in the '210 exemplifies the main reason why the trend in the industry has moved into the three-polysilicon structure for the fabrication of embedded memory cells.
As shown in FIG. 1 of the '210 patent, the capacitor in the DRAM cell is formed with two capacitors in parallel, the lower capacitor is the tunnel oxide dielectric film (16a and 16b) sandwiched by the 1st poly (18a and 18b) and the p+ diffusion region (15), and the upper capacitor is the oxide film (19a, b, c, d) and the oxide/nitride/oxide composite film (21a, b) sandwiched between the 1st poly and the 2nd poly (23a, b). The thin oxide (16a and 16b) serves as the tunnel oxide for the flash memory, and as one of the capacitor dielectric films. The 1st poly serves as the floating gate (FG) of the flash memory cell and as the common electrode for the lower and upper capacitors in the DRAM cell. The thin oxide in 19a, b, c, d is employed as the insulating layer between the poly1 edge sidewall and the poly2 in the capacitor region of the DRAM cell, the CMOS gate oxide of the DRAM cell, and the poly oxidation of the FG in the flash memory cell, respectively. The 2nd poly is doped as p-type to allow good contact with p+ diffusion region 15, it also serves as the top electrode for the upper capacitor and the CMOS poly gate, and as the control gate (CG) of the flash memory cell. The tunnel oxide, which serves as the capacitor dielectric of the lower capacitor, is grown on the p+ diffusion region. Since the tunnel oxide is usually very thin (typically between 60 .ANG. and 120 .ANG.) and has relatively poor quality and thickness control above the heavily doped region, the high leakage current from the lower capacitor (and, in turn, the entire DRAM capacitor) is expected to result in poor data retention. Also, the 2nd poly film overlaps the poly1 edge in the capacitor region, where poly1 sidewall oxide (19) is the only insulating layer between the two poly electrodes. Since the poly1 edge is expected to have the highest electric field whenever there is a voltage drop between the two poly electrodes, the poor quality of the oxide is typically not sufficient to ensure a low leakage capacitor. The situation becomes worsened in nonvolatile memory applications, which typically involve a high voltage drop across the capacitors. Furthermore, the 1 st poly, which serves as the FG for the flash memory, is not heavily doped in order to keep good quality of the tunnel oxide and the oxide/nitride/oxide. As a result, by using poly1 as the common electrode of the lower and the upper capacitors, the voltage coefficient of the capacitor is expected to be high. Additionally, in the '210 patent, poly2 has to be doped with p-type dopants in order to allow good contact with the p+ diffusion region. In other words, the CMOS gate in the '210 is p-type doped, and, as a result, the threshold voltage of the NMOS device is expected to be very large.